1. Technical Field
The present invention relates to a semiconductor device and a semiconductor device package, and more particularly, to a bump arrangement for a semiconductor device and a semiconductor device package including the same.
2. Description of the Related Art
In order to meet demands for increasingly light-weight, miniaturized, faster, multifunctional, and higher-capacity semiconductor products, the size of a semiconductor device must be decreased while increasing the number of pads on the device. One approach to accomplish this is shortening the pitch between neighboring pads. Ultimately, there is a limit to the number of pads that may be formed on an active surface of a semiconductor device when the device has a size restriction, though. Also, there is a minimum interval required for the pitch between neighboring pads because electrostatic malfunctions can occur between pads that are disposed in close proximity with an excessively small pitch. There is therefore a limit to the degree by which a semiconductor device can be miniaturized.
When considering these limitations, the size of a semiconductor device must naturally be increased to accommodate an increase in the number of its pads. From a manufacturing standpoint, this leads to a yield reduction in the number of semiconductor devices per wafer.
Also, an increase in the number of pads for a semiconductor device translates to an enlargement of the semiconductor device, which correlates to a finer pitch between wire patterns of a wiring substrate and an increase in size of the wiring substrate, thus increasing manufacturing costs of a semiconductor product.
Because making the pitch between wire patterns finer requires higher precision during manufacturing of a semiconductor device package, the assembly yield of the semiconductor device package decreases, and the manufacturing costs of the semiconductor device package increase.
One proposal for overcoming these problems and arranging a maximum number of pads at a minimum pitch is a staggered arrangement of the pads.
FIG. 1A is a plan view illustrating a bump arrangement of a typical semiconductor package, and FIG. 1B is an enlarged view of portion A of FIG. 1A.
Referring to FIGS. 1A and 1B, a semiconductor device package that has a semiconductor device 20 inner lead bonded (ILB) to a wiring substrate 10 may be a chip-on-board (COB) type package.
The semiconductor device 20 may have a bump arrangement in which first and second bump columns 22a and 22b are alternately arranged from the edge toward the center of an active surface of the semiconductor device 20. The first and second bump columns 22a and 22b may be arranged in a staggered formation.
Leads 12a and 12b of the wiring substrate 10 may correspond to the first and second bump columns 22a and 22b of the semiconductor device 20. The leads 12a and 12b may include first bump column leads 12a and second bump column leads 12b that respectively correspond to the first bump column 22a and the second bump column 22b. 
To align the first and second bump columns 22a and 22b correspondingly with the first and second bump column leads 12a and 12b, the semiconductor device 20 is disposed in a mounting region of the wiring substrate 10, after which the semiconductor device 20 may be mounted on the wiring substrate 10 by applying heat and pressure. Thus, the first and second bump columns 22a and 22b may be electrically connected to the first and second bump column leads 12a and 12b. 
When the pitch between leads is uniform in the above two-column staggered formation of bumps, there is a limit to the amount by which the size of the bumps can be increased. Thus, because there is little difference between the sizes of the bumps and leads, aligning errors can occur in which leads deviate from corresponding bumps during bonding between the bumps and leads in the manufacturing of semiconductor device packages.
As an alternative to the above described package, a bump arrangement in which many more bumps are provided in a second bump column than in a first bump column has been proposed. However, this arrangement has the limitation of reducing the flow of molding material during the process of mounting a semiconductor device on a wiring substrate. Therefore, this arrangement also does not provide a suitable solution.
The present invention addresses these and other disadvantages of the conventional art.